Path Exceptions

 Multi-cycle paths:

A multi-cycle path is one in which data launched from one flop is allowed (through architecture definition) to take more than one clock cycle to reach to the destination flop.

Why multi-cycle paths are introduced in designs: 

A typical System on Chip consists of many components working in random. Each of these works on different frequencies depending upon performance and other requirements. Ideally, the designer would want the maximum throughput possible from each component in design with paying proper respect to power, timing and area constraints.

In case my combinational data path delay is such that it takes 3 clock cycles to propagate the data to capture flop then there should be multi cycle path (mcp) defined for setup check as

set_multicycle_path 3 -setup -from [get_pins <launch_flop>/Q] -to [get_pins <capture_flop>/D]

The important point to be note here is that if i have not to defined the corresponding mcp constrain for hold then the default hold check applies and it says that this check will happen one cycle prior to the setup check (with mcp). so if a clock period is 5ns and i have applied the above constraint then setup check will happen at 15ns and the default hold will be checked at 10ns (one cycle prior to 15ns). Please refer below.

The combo in the path takes delay upto 3 clock cycles.

              Now what is the problem with constraint defined above is . we have provided mcp constraint for setup but corresponding constraint for hold is missing. The intended hold check should be done at the same launch edge. so the corresponding hold constraint will be,

set_multicycle_path 2 -hold -from [get_pins <launch_flop>/Q] -to [get_pins <capture_flop>/D]

So in general in most of the designs, a mcp of setup of 'N' clock cycles should be provided with corresponding mcp hold with '(N-1)' clock cycles. What happens when a multi-cycle setup of N is specified but the corresponding N-1 multi-cycle hold is missing? In such a case, the hold check is performed on the edge one cycle prior to the setup capture edge.

The designer may think to introduce multi-cycle paths in the design in one of the following scenarios:

1. Very large data-path limiting the frequency of entire component

2. Paths starting from slow clock and ending at fast clock

         set_multicycle_path 2 -setup -from ff1/Q -to ff2/D -end

                      set_multicycle_path 1 -hold   -from ff1/Q -to ff2/D -end

3. Paths starting from fast clock and ending at slow clock

                

         set_multicycle_path 2 -setup -from ff1/Q -to ff2/D -start

                      set_multicycle_path 1 -hold   -from ff1/Q -to ff2/D -start

Optimization engine will know about a path being multi-cycle only when it is told through SDC commands in timing constraints. If we dont specify a multi-cycle path as multicycle, optimization engine will consider it as a single cycle path and will try to use bigger drive strength cells to meet timing. This will result in more area and power; hence, more cost. So, all multicycle paths must be correctly specified as multi-cycle paths during timing optimization and timing analysis.