Physical Design Introduction

•  Structural Representation to Physical Implementation i.e., Netlist to GDSII. Physical design directly impacts circuit performance, area, reliability, power, and manufacturing yield.
• Performance: Long routes have significantly longer signal delays.
• Area: Placing connected modules far apart results in larger and slower chips.
• Reliability: A large number of vias can significantly reduce the reliability of the circuit.
• Power: Transistors with smaller gate lengths achieve greater switching speeds at the cost of higher leakage current and manufacturing variability. Larger transistors and longer wires result in greater dynamic power dissipation.
• Yield: Wires routed too close together may decrease yield due to electrical shorts occurring during manufacturing, but spreading gates too far apart may also undermine yield due to longer wires and a higher probability of opens.

• Stages
• Placement and Routing (PnR)
• Signoff

• Objectives
• Timing
• Congestion
• Area
• Power

• Possible Issues
• Timing Violations
• Congestion Issues
• Design Rule Violations