FloorPlan VLSI

            A floorplanning is the process of placing blocks/macros in the chip/core area, thereby determining the routing areas between them. Floorplan determines the size of die and creates wire tracks for placement of standard cells. It creates PG connections. It also determines the I/O pin/pad placement information.

      Before we are going for the floor planning to make sure that the inputs are used for floorplan is prepared properly. After physical design database creation using imported netlist and corresponding library and technology file, steps to done are :  

1. Decide core width and height for die size estimation.
2. IO pad sites are created for placement of IO pad placement.
3. Placement of macros.
4. The standard cell rows created for standard cell placement.

        Apart from this aspect ratio of the core, utilization of core area, cell orientation and core to IO clearance are also taken care of during the floorplan stage.

Types of Floorplan Techniques

• Abutted floorplan : Channel less placement of blocks.
• Non-Abutted Floorplan : Channel based placement of blocks.
• Mix of both: partially abutted with some channels.

Terminologies and Definitions 

Aspect ratio:  

• Aspect ratio will decide the size and shape of the chip. It is the ratio between horizontal routing resources to vertical routing resources (or) ratio of height and width.    
• Aspect ratio = width/height 

Utilization :

• Area of the core that is used for placeing Standard Cells and Macros expressed in percentage. core utilization = (macros area + std cell area +pads area)/ total core area

Manufacturing Grid :

• The smallest geometry that semiconductor foundry can process or smallest resolution of your technology process (e.g. 0.005)
• All drawn geometries during Physical Design must snap to this grid
• While Masking fab. use this as reference lines

Standard Cell Site/ Standard Cell Placement Tile/ Unit Tile :

• The minimum Width and Height of a Cell that can occupy in the design
• The Standard Cell Site will have the same height as Standard Cells, but the width will be as small as our smallest Filler Cell.
• It’s one Vertical Routing Track and the Standard Cell Height
• All Standard Cells must be multiple of Unit Tile

Standard Cell Rows :

• Rows are actually the Standard Cell Sites abut side by side and then Standard Cells are placed on these Rows
• Cells with the equal no. of Track definition will have same height

Placement Grid :

• Placement Grid is made up of Standard Cell Site
• Its always a multiple of Manufacturing Grid
• Placement Grid is made up of the Rows which are composed of Sites

Routing Grid and Routing Track :

• Horizontal and Vertical line drawn on the layout area which will guide for making interconnections
• The Routing Grid is made up of the Routing Tracks
• Routing Tracks can be Grid-based, Gridless based or Subgrid-based

Flight-line/ Fly-line :

• Virtual connection between Macros and Macro or Macros and IOs
• This helps the designer about the logical connection between macros and pads. 
• Fly lines act as guidelines to the designer to reduce the interconnect length and routing resources.

Macro :

• Any instances other than Standard Cell and is as loaded as black box to the design is Macro.
• Intellectual Property (IP) e.g. RAM, ROM, PLL, Analog Designs etc.
• Hard Macro: The circuit is fixed. We can’t see the functionality information about macros. Only we know the timing information. IP with Layout implemented
• Soft Macro: The circuit is not fixed and we can see the functionality and which type of gates are using inside it. Also we know the timing information. IP without Layout implemented (HDL)

Guidelines to place macros::

• Placement of macros are the based on the fly-lines ( its shows the connectivity b/w macro to macro and macro to pins) so we can minimize the interconnect length between IO pins and other cells.
• Place the macros around to the boundary of the core, leaving some space between macro to core edge so that during optimization this space will be used for buffer/inverter insertion and keeping large areas for placement of standard cells during the placement stage.
• Macros that are communicating with pins/ports of core place them near to core boundary.
• Place the macros of same hierarchy together.
• Keep the sufficient channel between macros. channel width = (number of pins * pitch )/ number of layers either horizontal or  vertical 
• Avoids notches while placing macros, if anywhere notches is present then use hard blockages in that area.
• Keep keep-out margin around the four sides of macros so no standard cells will not sit near to Macro pins. This technique avoids the congestion.
• Keep placement blockages at the corners of macros.
• For pin side of macros keep larger separation and for non-pin side, we can abut the macros with their halo so that area will be saved and Halo of two macros can abut so that no standard cells are placed in between macros.
• Between two macros at least one pair of power straps (power and Ground) should be present.
• Lots of iterations happen to get optimum floorplan, the designer takes care of the design parameter such as power, area, timing and performance during floorplanning.

Issues arises due to bad Floorplan:

• Congestion near Macro Pins/ Corners due to insufficient Placement Blockage
• Std. Cell placement in narrow channels led to Congestion
• Macros of same partition which are placed far apart can cause Timing Violation
  
  
  

Floorplan Qualification:

• No I/O ports short
• All I/O ports should be placed in routing grid
• All macros in placement grid
• No macros overlapping
• Check PG connections (For macros & pre-placed cells only)
• All the macros should be placed at the boundary
• There should not be any notches. If unavoidable, proper blockages has to be added
• Remove all unnecessary placement blockages & routing blockages (which might be put during floor-plan & pre-placing)

Floorplan outputs

• IO ports placed
• cell rows created
• macro placement final
• core boundary and area
• pin position
• floorplan def

Important questions related to floorplan :

1. What are the inputs and outputs for floorplan ?

Floorplan inputs

• Technology file
• Netlist
• SDC
• Library files (.lib & .lef)
• TLU+ file 

Floorplan outputs

• IO ports placed
• cell rows created
• macro placement final
• core boundary and area
• pin position
• floorplan def

2. What are the types of floorplan ?

• Abutted floorplan : Channel less placement of blocks.
• Non-Abutted Floorplan : Channel based placement of blocks.
• Mix of both: partially abutted with some channels.

3. Types of placing standard cell rows?

4. What are floorplan control parameters ?

5. What are different steps involved in floorplan?

6. What are macro guidelines 

If two communicating macros placed close to each another and if all the pins of both the macros are connected to each other than there is no need of spacing but if some pins are talking with the core logic than we need to provide some spacing so that from the pin route should come and connect to the logic. So minimum spacing required between the 2 macros or boundary and macro is called as the channel.

7. What is core utilization ?

It is the ratio of (std cell area + macro area + blockage area) / total area

8. What is cell utilization ?

It is the ratio of std cell area/ total area allocated to standard cells

9. What is gate count?

Gate count is 3 to 4 times of instance count.

Total placeable instance area / 2 input NAND gate area in .lib

10. What is aspect ratio ?

It is the ratio of vertical routing resources to the horizontal routing resources.

11. What is a channel ?

It is the minimum spacing required between two macros or between macros and boundary.

12. How do you calculate the channel width ?

Based on the fly-line analysis we will able to know the no. of signals passing through the channel and suppose “21” signals are passing than “21” metal routes are required. So if the signal are need to be routed vertically than we divide the no of routes by no of vertical layers. Suppose no of vertical layers is “3”. On each metal layer 7 track are needed so the width of channel should be equal to 7 tracks.

13. How do you measure the no. of signals passing through a channel ?

Through the fly-line analysis

14. How do you calculate the the metal routes that can be passed through a channel ?

The no of metal routes required is equal to the no of signal passing through the channel