Sanity Checks

 Sanity Checks :

To ensure that the input received from the library team and synthesis team is correct or not. If we are not doing these checks then it creates problems in later stages of design.

Basically, we are checking following input files: and make sure that these files are complete and not erroneous.

•         Design/netlist checks
•          SDC checks
•          Library checks

Design checks: Check if current design is consistent or not. It checks the quality of netlist and identifies:

•        Floating pins : unconnected pins
•        Multidriven nets :

o   Multi-driven nets can be created in the RTL by introducing drivers of same or different signal strengths. However, driving a net with multiple signals are not considered as good design practice. This could lead to a failure in post silicon verification as the driver strengths can potentially get heavily altered due to manufacturing defects.

o   Many EDA tools do not allow multi-driven nets in the design, and the designers are expected to remove all multi-driven nets from the design.

•          Undriven input ports
•          Unloaded outputs
•          Unconstrained pins
•          Pin mismatch counts between an instance and its reference
•          Tristate buses with non-tristate drivers
•          Wire loops across hierarchies
•         Constant hierarchical pins :

o   Constant hierarchical pins are generally not a problem, but they are still worth investigating.

o   When RC propagates constants across hierarchical boundaries, it will tie the pin to 1'b0.  The other side of that hierarchical pin will have nothing attached to it.  It effectively becomes an unused hierarchical pin, but RC, by default, will tie it off so it is not undriven.

o   What we need to do, is to run "check_design -constant" and look at any constant hierarchical pins have a fanout greater than 0.  A fanout of 0 means that it is an unused hier pin, which is not an issue.

o   In this case, some of the JTAG_MODULE pins are tied off, which I expect, and all the rest of a fanout of 0 are not a problem here.

ICC command: check_design

SDC Checks : If any unconstrained paths exist in the design then PNR tool will not optimize that path, so these checks are used to report unconstrained paths

•        Checks whether the clock is reaching to all the clock pin of the flip-flop.
•         Check if multiple clock are driving same registers
•         Check unconstrained endpoints
•         Port missing input/output delay.
•         Port missing slew/load constraints.

ICC command: check_timing

Library checks: It validate the library i.e. it checks the consistency between logical and physical libraries. It checks the qualities of both libraries. This library checks shows

•         Name of the library
•         Library type & its version
•         Units of time
•         Capacitance
•         Leakage power
•         Current
•         Number of cells missing
•         Number of metal or pins missing in the physical and logical library.

ICC command : check_library