Clock Tree Synthesis

CTS is the process of inserting buffers/inverters along the clock paths to balance the clock delay to all clock inputs. So in order to balance the skew and minimize insertion delay, we are doing CTS.

Inputs for CTS:

• Detailed placement DB
• Target for latency and skew , buffers/inverters for building the clock tree
• Clock Tree DRC (Max Tran, Max Cap, Max Fanout, Max number of levels)

Outputs of CTS:

• Database with properly build clock tree in the design

Checklist after CTS:

• Skew Report
• CLock tree report
• Timing reports for setup and hold 
• power and area reports

Why clock routes are given more priority than signal nets?   

Clock is propagated after placement becoz the exact physical location of cells and modules are needed for the clocks propagation which in turn impacts in dealing with accurate delay and operating frequency and clock is propagated before routing becoz when compared to signal routes, clock routes are given more priority. This is becoz clock is the only signal switches frequently which in turn acts as source for dynamic power dissipation.

Difference between clock buffer and normal buffer ?

A buffer is an element which produces an output signal, which is of the same value as the input signal.

Clock buffers are designed specifically to have specific properties that are supposed for clock tree distribution. When compared to normal buffers, clock buffers have

• equal rise and equal fall times
• less delays variations with PVT and OCV

Usually in soc’s clock routing is done in higher metal layers as compared to signal routing . So to provide easier access to clock pins from these layers, clock buffers may have pins in higher metal layers. For normal buffers the pins are expected to be in lower metal layers only.

Clock buffers are balanced in other words rise and fall times of clock buffers are nearly equal, the reason behind this is that if the clock buffers are not balanced there will be duty cycle distortion in the clock tree, which can lead to pulse width violations. Compare to normal buffers, clock buffers have high drive strength, due to this it can drive long nets and can have higher fanouts. This help clock buffers and hence to have overall delays.

What is the merits and demerits of clock buffers and clock Inverters ?

Effects of CTS:

• Clock buffers and clock inverters are added.
• Congestion and Timing violations may increases

Clock Skew :

• Keeping clock skew to a minimum is considered to be a good measure of CTS.
• Clock skew is nothing but difference between 2 flops in arrival times of clock signal at the respective clock pins. 
• Clock skew = (arrival time at capture clock pin) - (arrival time at launch clock pin)
• If clock arrival time at capture flipflop is greater than arrival time of launch flipflop , then it is called as positive clock skew. (due to this hold violations occur)
• If clock arrival time at launch flipflop is greater than arrival time of capture flipflop , then it is called as negative clock skew. (due to this setup violations occur).
•