Physical Design Flow

PHYSICAL DESIGN:

        Physical design means netlist (.v) converted into GDSII form (layout form). In other words logical connectivity of cells converted into physical connectivity.

IMPORT  :

            All design related inputs like .v, .libs, .lefs, .sdcs and .upf are read by the tool. After importing all the input files we perform sanity checks like check_design, check_timing to know the netlist related issues. At this stage we need to check that timing is comparable with the synthesis results.

FLOOR PLANNING :

           Based on the flylines analysis and hierarchical family, macros are arranged towards the boundary of the design. We also add blockages like soft, hard and partial blockages or density screens to remove the congestion.

POWER PLANNING :

        Power mesh is build by using the top metal layers on the entire design. Power grid network is created to distribute power to each part of the design equally. Three levels of power distribution

• Rings : Carries VDD and VSS around the chip
• Stripes : Carries VDD and VSS from rings across the chip
• Rails : Connect VDD and VSS to the standard cell VDD and VSS

Power plan mainly involves placement of :

• Core power ring
• Vertical & Horizontal power stripes in the core
• Standard cells power hookup
• Block power hookup
• IO power hookup

PRE-PLACEMENT :

            At this stage Well-tap cells and End-cap cells  are inserted in our design.

PLACEMENT: 

            Actual placement of standard cells is done. Placement is the process of finding a suitable physical location for each cell in the block. Placement does not just place the standard cell available in the synthesized netlist, it also optimized the design.

CLOCK TREE SYNTHESIS:

         CTS is the process of connecting the clocks to all clock pin of sequential circuits by using inverter/buffers in order to balance the skew and to minimize the insertion delay. Clock balancing is important for meeting all the design constraints.

ROUTING:

            Routing is the actual stage after CTS and optimization where exact paths for interconnection of standard cells and macros and I/O pins are determined.