Difference between clock buffer and normal buffer ?
A buffer is an element which produces an output signal, which is of the same value as the input signal.
Clock buffers are designed specifically to have specific properties that are supposed for clock tree distribution. When compared to normal buffers, clock buffers have
Usually in soc’s clock routing is done in higher metal layers as compared to signal routing . So to provide easier access to clock pins from these layers, clock buffers may have pins in higher metal layers. For normal buffers the pins are expected to be in lower metal layers only.
Clock buffers are balanced in other words rise and fall times of clock buffers are nearly equal, the reason behind this is that if the clock buffers are not balanced there will be duty cycle distortion in the clock tree, which can lead to pulse width violations. Compare to normal buffers, clock buffers have high drive strength, due to this it can drive long nets and can have higher fanouts. This help clock buffers and hence to have overall delays.
What is difference between set_disable_timing and set_false_path ?
Set_disable_timing is generally useful to disable a particular arcs within the cell. Set_disable_timing and set_false_path both restrict the timing analysis of a particular path but the difference is that with set_false_path still the path delay will be calculated but will not be reported where as set_disable_timing will remove the timing path from analysis.
How timing of other groups will be affected when input/output delay is changed ?
If set_input_delay and set_output_delay is reduced it will improve in2reg and reg2out timing. It will not have any impact on reg2reg timing. Output delay is subtracted from the clock period and you have to meet reg2out path in remaining time. If output delay is less, you get more time to meet reg2out path. Similar thing is applicable for input delay.
If a timing path is not reported in a prime time what could be the cause or how you will debug that path?
If a intended timing path is not shown in prime time, this could be due to constraint problem. Either the path is unconstrained (which anyways will be shown in timing shell) or due to some applied exception which is blocking the path from being reported. In such scenario analyze_path command can be used which identifies timing exception and constraints on a particular timing path (cause of blockage).
How would you check for your constraints coverage for a big design?
Many designs have numerous and vast set of constraints. In a multi-mode multi-corner design it is very hard to find the constraint coverage, it means whether you have covered your design with full set of constraints or not. report_analysis_coverage command is used to check the coverage of constraints. This command basically check whether your end point (or timing arc) is tested or not. The end point is tested for the following checks setup and hold, min_pulse_width, min_period, clock_gating_check etc. PT generates a detailed report giving the list of tested and untested checks. with this report one can easily debug on the constraint part.
How max_transition violations are fixed?
max_tran is a highest priority drc check. If the trans is bad (or more) then it will lead to large delays and also will impact the dynamic (switching) power. Usually clock nets should have minimum transition values. Trans violation can be fixed by buffering the net, Up-sizing the driver cell, decreasing the spacing between cells or decreasing the wire length.
How you will find the virtual clock period corresponding to the input/output ports (which need to be constrained) when external design parameters (connected block info) are not known?
When external I/O info is not available specially for the clock, then in this case the fanout of input port can be traced (upto level 1 flop) for endpoint. After getting the info of connected flop to the port, the clock information of flop can be easily obtained and the same clock period can be used as period of virtual clock to constraint the input port.
How Synthesis results will change when max_transition value is changed. (as compared to the original runs)
When max_trans value is changed with respect to the original value, this will impact the synthesis results like switching power, delay. max_transition time signifies the time which a signal takes to change its state. A slow input transition time (more time) will slow the rate at which the cell’s transistors can change state logic 1 to logic 0 (or logic 0 to logic 1), thereby increasing the delay of the logic gate. Also if the transition time is more then it means the time for which both the transistors turn-on is also more which leads to more switching power. so synthesis results mainly delay and power will change accordingly.
What should be done if you are seeing big violations in timing reports after synthesis. or in other words how to fix timing violations after synthesis.
Generally after synthesis one should check the timing reports (pre-sta reports). If you are seeing a big setup violations then,
One should look for the missing constraints (if-any) like multi-cycle path, false path etc.
Its always recommended to start the synthesis with high-Vt (HVT) cells so as to reduce the leakage power. If you are able to close the timing with the HVT cells then its ok otherwise open LVT cells during synthesis, this will help in reducing the timing violation.
Another method is creating path groups. We can create path groups and assign weightage to those path so that tool will try to fix them separately.
Specify critical range: If we don't specify critical range, it works only on WNS but if critical range is specified then it works on all path which are below the specified range and it reduces TNS also.
Enable boundary optimization, but it optimize area also.
Try incremental compile (with high effort).
Enable register retiming: Register retiming is the process by which the tool moves registers through combinational gates to improve timing.
Pipeling.
Remove area constraints (if any).
How Wire-load delay model (WLM) works.
A wire-load model is what the synthesis tool uses to estimate wire characteristics (e.g. interconnect delay) in the absence of physical layout data. For a wire with a given fanout, the wire-load model specifies the capacitance, resistance, and area of the wire.
What you generally check when synthesis is over.
When synthesis is over one should check for the QoR report, which will give a snapshot of various timing details, area info, power info etc. Ideally there will be different detailed reports generated for area (sequential/combinational count), timing (clock group wise TNS, WNS) and power. There are some sanity checks also which should be performed in the generated netlist like modal coverage, no-clock/multi-clock report etc to check the correctness of netlist.
What are timing loops?
When you have the timing path from output to input again through some combinational cells, then it creates a timing loop.
How to break a timing loop?
Using set_disable_timing, or manually doing disconnect and connect.
What are different timing arcs in a Flop ?
D--> CLK and CLK --> Q
What happens to a flop when you have the D --> Q defined as timing arc?
The flop will work as a computational cell, Probably as a buffer.
What is ground bounce effect ?
The noise produced by simultaneously switching output buffers. Then due to this it cant properly discharge through vss. It will change the voltage levels of power/ground nodes and is so-called “Ground Bounce Effect”.
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