Synthesis

•  The process of parsing, translating, optimizing and mapping RTL code into a specified standard cell library. 
• To determine the feasibility of the design , we need to synthesize the RTL code into specific gate level netlist (includes nets.cells & their connectivity) and measure timing, power & area , before moving on to placement .
• Goals of synthesis:
• To get gate level netlist
• Inserting clock gates
• Logic optimization
• Inserting DFT logic
• Logic equivalence between RTL and netlist should be maintained
• Inputs required:
• Tech related :
• .tf file (physical aware synthesis)
• Floorplan def (physical aware synthesis)
• .lib file
• Design related
• .v file
• .SDC file
• Synthesis flow :
• Reading the design,
• Setting constraints,
• Optimizing the design,
• Analyzing the results &
• Saving the design database.

Synthesis Overview (script.tcl)

Synthesis include the following main tasks: reading in the design, setting constraints, optimizing the design, analyzing the results and saving the design database. These tasks are described below.

*******Reading in the design: analysing and elaborating**********

*Analyse command performs the following tasks:

1.Read the HDL source and checks it for syntactical errors

2.Creates HDL library objects in an HDL independent intermediate format and saves the intermediate files in a specified location. If we analyse reports errors, they must be fixed and the design re-analysed before continuing

*Elaboration command (elaborate) does 

Translation: RTL code is translated to technology independent representation(GTECH). The converted logic is available in boolean equation form.

Check the elaboration reports carefully to see the number, the type of memory elements, unresolved references exist in our design.

At this point, if the elaboration completed successfully, the design is represented in GTECH format, which is an internal, equation-based, technology-independent design format.

********Constraining the design**************************

The next task is to set the design constraints. Constraints are the instructions that the designer gives to tool. They define what the synthesis tool can or cannot do with the design or how the tool behaves.

2 types of design constraints:

###Design Rule Constraints#######

Design rules constraints are implicit constraints which means that they are defined by the ASIC vendor in the technology library. By specifying the technology library that synthesize tool should use.

*Maximum transition time: Longest time allowed for a driving pin of a net to change its logic value

*Maximum fanout: Maximum fanout for a driving pin

*Maximum (and minimum) capacitance: The maximum (and minimum) total capacitive load that an output pin can drive. The total capacitance comprises of load pin capacitance and interconnect capacitances.

*Cell degradation: Some technology libraries contain cell degradation tables. The cell  degradation tables list the maximum capacitance that can be driven by a cell as a function of the transition times at the inputs of the cell.

###Optimization Constraints####

Optimization constraints are explicit constraints set by the designer. They describe the design goals (area and timing). As per that constraints tool need to perform synthesis.

*System clock definition & clock delays: Clock constraints are the most important constraints in your ASIC design. The clock signal is the synchronization signal that controls the operation of the system. The clock signal also defines the timing requirements for all paths in the design. Most of the other timing constraints are related to the clock signal.

*Multicycle paths: A multicycle path is an exception to the default single cycle timing requirement of paths. That is, on a multicycle path the signal requires more than a single clock cycle to propagate from the path startpoint to the path endpoint.

*Input and output delays: Input and output delays constrain external path delays at the boundaries of a design. Input delay is used to model the path delay from external inputs to the first registers in the design. Output delay constraint the path from the last register to the outputs of the design.

*Minimum and maximum path delays: Minimum and maximum path delays allow constraining paths individually and setting specific timing constraints on those paths.

*Input transition and output load capacitance: These constraints can be used to constrain the input slew rate and output capacitance on input and output pins.

*False paths: A false path is a path that cannot propagate a signal. For example, a path that is not activated by any combination of inputs is a false path.

Note that synthesis tool tries to meet both design rule and optimization constraints but design rule constraints always have precedence over the optimization constraints. This means that tool can violate optimization constraints if necessary to avoid violating design rule constraints.

**********Optimizing the Design**********

The optimization step finally translates the HDL description into gate-level netlist using the cells available in the technology library. The optimization is done in several phases. In each optimization phase different optimization techniques are applied according to the design constraints. 

Synthesize tool performs optimizations on three levels: architectural, logic-level, and gate-level.

######Architectural Optimizations#########

Architectural optimizations are high-level optimizations which are performed on the HDL description level. These optimizations include tasks such as:

#Arithmetic Optimizations: Arithmetic optimization uses the rules of algebra to improve the implementation of the design. That is, synthesis tool may rearrange the operations in arithmetic expressions according to the constraints to minimize the area or timing.

#Resource Sharing: Resource sharing tries to reduce the amount of hardware by sharing hardware resources with multiple operators in your HDL description. For example, single adder component may be shared with multiple addition operators in the HDL code. Without resource sharing each operator in your code will result as a separate HW component in the final circuitry.

#Selecting DesignWare Implementations: Selecting a DesignWare implementation means that the implementation selection of a particular resource is left to the synthesis tool. For example, the Basic IP Library contains two implementations (ripple and carry-lookahead) for the +-operator (the DesignWare Foundation Library provides more implementations for the '+' and other operators). When selecting DesignWare implementation, Tool considers all available implementations and makes it selection according to your constraints.

At this point, the design is represented by GTECH library parts (i.e. generic, technology-independent netlist).

########Logic-level Optimizations########

Logic-level optimizations are performed on GTECH netlist and consists of two processes: structuring and flattening.

#Structuring: Structuring evaluates the design equations represented by the GTECH netlist and tries by using Boolean algebra to factor out common subexpressions in these equations. The subexpressions that have been identified and factored out can then be shared between the equations. For example, Before Structuring After Structuring

P = ax + ay + c 

P = aI + c

Q = x + y + z 

Q = I + z

I = x + y

Structuring is usually recommended for designs with regular structured logic.

#Flattening: Flattening tries to convert logic into two-level, Sum-of-Products representation. Flattening produces fast logic (by minimizing the levels of logic between the inputs and outputs) at the expense of the area increase. Flattening is recommended for designs containing unstructured or random logic.

########Gate-level Optimizations########

Gate-level optimizations work on the technology-independent netlist and maps it to the library cells to produce a technology-specific gate-level netlist. Gate-level optimizations include the following processes:

1.Mapping: Mapping to the technology library and performing incremental optimization

syn_map command maps the specified design to the cells described in the supplied technology library and performs logic optimization

The 3 main steps performed in syn_map command are:

a.Technology independent Boolean optimization (Optimization): Boolean equation is optimized using SoP or PoS optimization methods.

b.Technology mapping: Technology independent boolean logic equations are mapped to technology dependent library logic gates based on design constraints, library of available technology gates.  This produces optimized gate level representation which is generally represented in verilog.

c.Technology-dependent gate optimization (IOPT ): The final optimization Genus performs is incremental optimization. Optimizations performed during IOPT improve timing and area and fix DRC violations.

Optimizations performed during this phase include multibit cell mapping, incremental clock gating, incremental retiming, tie cell insertion, and assign removal.

syn_opt command is used for optimization.

2.Delay Optimization: Delay optimization fixes the timing violations introduced by mapping phase.

3.Design Rule Fixing: Design rule fixing fixes the design rule violations in the design. Basically this means that the tool inserts buffers or resizes existing cells. Note that design rule fixing phase is allowed to break timing constraints.

4.Area Optimization: Area optimization is the last step that Design Compiler performs on the design. During this phase, only those optimizations that don't break design rules or timing constraints are allowed.