Inputs of Physical Design

PHYSICAL DESIGN :

                It is the process of transforming netlist into physical layout, which describes the position of cells and routes the interconnection between them.

Inputs for Physical Design :

1. Gate level netlist (.v)
2. Timing, Logical & Power libraries (.lib or .db)
3. Physical library (.lef)
4. Technology file (.tf)
5. TLU + file (.TLUP)
6. Synopsys Design constraints (.sdc)
7. Power specification file (.upf or .cpf)

Name of Inputs	File  format	Given by
Netlist	.v (Verilog)	Synthesis team
SynopsysDesign Constraints  (SDC)	.sdc(written in TCL)	Synthesis team
Timing library / Logical library	.lib(liberty  file)	Vendors
Physical library	.lef (layout exchange format)	Vendors
Technology file	.techlef / .tf	Foundry
TLU+(Table Look Up)	.tlup	Foundry

Gate level netlist (.v) :

• Once we synthesize RTL, we will see only gates where connections make the intended logic what we coded in RTL. Since whatever we write in RTL eventually it must be converted to basic gates (no matter how complex algorithm).
• It contains logical connectivity of all cells (standard cells & macros) and also contains the list of nets (in the design for knowing connectivity by using Fly lines).
• example of netlist:
• module and_gate(y,a,b);
• input a,b;
• output y;
• AND2 U1(.Y(y), .A(a), .B(b));
• endmodule

Timing, Logical & Power libraries (.lib) :

• It is generally a .lib/.db file that contains timing & functionality information of all the standard cells, soft macros and hard macros, also design rules like max transition, max capacitance and max fanout.
• It consists of cell delays, setup and hold in timing information whereas functionality information is used for optimization purpose. 
• It also contains power information like leakage power for default cell, input and output voltage.
• PVT corners are also present. for every PVT corner the timing of cells is different. Hence for every PVT corner there is a .lib file present.
• Cell delay is a function of input transition and output load and is calculated based on lookup tables.
• Cell delays are calculated by Nonlinear Delay Model(NLDM) and composite current source (CCS) models.

            

CCS(Composite current source)	NLDM (Non-Linear Delay Model)
It’s like Norton equivalent circuit	It’s like Thevenin's equivalent circuits
current source used for driver modeling	Voltage source used for driver modeling
It 20 variables to account input transition and output load	It has only 2 variables.
CCS is more accurate	Less accurate
CCS file is 10x times larger than NLDM because of more numbers of variables	Smaller than CCS file
Runtime for CCS is more	Runtime is less

Physical library (.lef) :

• It is a file consists of physical information of standard cells & macros.
• pin information
• Height and minimum width of the placement rows.
• Preferred routing directions
• Pitch of routing tracks.
• And also it contains 2 views
• cell view : useful at the time of tapeout.
• fram view (abstract view) : useful at the time of place & route.
• Example of lef:
                               layer M2
                               type routing
                                width 0.50;
                                end M2
                                layer via
                                  type cut
                                end via
                                macro AND_1
                                      origin 0.000
                                      size 4.5 by 12
                                      symmetry x y;
                                      site core;
                                 pin A 
                                     dir input;
                                      port 
                                      layer M2
                                  end 

Technology file (.tf) : 

• It contains name and number convention of metal layer and via information.
• It contains physical, electrical characteristics & physical design rules of metal layer and via.
• In physical characteristics:- min width , area, height are present
• In electrical characteristics:- current density is present
• Physical design rules like wire to wire spacing, min width between layer and via are present
• Units and precisions of layer and via
• Colors and pattern of layer and via

TLUplus (.tlup) :

• RC parasitics of metal per unit length. These values are used for calculating net delays.
• If tlu+ files are not given then these values are taken from .itf file.
• For loading TLU+ files we have to load 3 files i.e., Max tlu+, Min tlu+ , Map file
• Map file maps the .ITF file and .tf file of the layer and via names
• It is a table containing wire cap at different net length and spacing.
• Milkyway.tf also contain parasitics model of wire as TLU+ contains. If you specify in ICC the TLU+ files then ICC used TLU+ files and did not read parasitics from .tf. if not specified by default ICC will use .tf.
• Advantage of TLU+ :
• More accurate
• Different TLU+ for different RC corners and scenario.
• Disadvantage of Milkyway.tf : 
• It is used only for one RC corner.

Synopsys Design Constraints (.sdc) :

• Timing constraints like clock definition, timing expections (false paths, multi cycle paths, half cycle paths, disable timing arcs, case analysis & asynchronous paths).
• Delay constraints like latency, Input delay, Input transition, output load, output transition, min delay and max delay.
• Power and area constraints
• Design rule constraints like Max fanout, Max cap & Max transition
• Clock uncertainity
• Operating conditions.

Power specification file (.cpf or .upf) :

• Power domains or ON/OFF regions
• PG nets