FinFet Technology

                 Modern FinFETs are 3D structures as shown in the Figure (a) also called tri-gate transistor. FinFETs can be implemented either on bulk silicon or SOI wafer. This FinFET structure consists of thin (vertical) fin of silicon body on a substrate. The gate is wrapped around the channel providing excellent control from three sides of the channel. This structure is called the FinFET because its Si body resembles the back fin of a fish.

                                            Figure (a) Fin-FET Structure

                In bulk-MOS (planner MOS), the channel is horizontal. While in FinFET channel, it is vertical. So for FinFET, the height of the channel (Fin) determines the width of the device. The perfect width of the channel is given by Equation.

            Width of Channel = 2 X Fin Height + Fin Width (Equation) 

            The drive current of the FinFET can be increased by increasing the width of the channel i.e. by increasing the height of the Fin. We can also increase the device drive current by constructing parallel multiple fins connected together as shown in the Figure (b). It implies that for a FinFET, the arbitrary channel width is not possible, since it is always a multiple of fin height. So, effective width of the device becomes quantized. While in planner devices, there is the freedom to choose the device’s drive strength by varying channel width.

                                            Figure 10. Multi-Fin FinFET Structure

                In conventional MOS, a doping is inserted into the channel, reducing the various SCEs and ensuring high V_th. While in FinFET, the gate structure is wrapped around the channel and the body is thin, providing better SCEs (short channel effect), so channel doping becomes optional. It implies that FinFET suffers less from dopant-induced variations. Low channel doping also ensures better mobility of the carriers inside the channel. Hence, higher performance. One thing noticed over here is that both FinFET and SOI technologies have introduced Body Thickness as a new scaling parameter.

               FinFET technology provides numerous advantages over bulk CMOS, such as higher drive current for a given transistor footprint, hence higher speed, lower leakage, hence lower power consumption, no random dopant fluctuation, hence better mobility and scaling of the transistor beyond 28nm.

              In comparison to SOI, FinFET has higher drive current. Moreover in FinFET, the strain technology can be used to increase carrier mobility.

                    One of the downsides of FinFET is its complex manufacturing process. According to Intel, the cost of FinFET manufacturing can increase by 2-3% over bulk.