Synthesis Q/A

 What are unconstrained end points? What will you do for that?

 Unconstrained end points are D pins, output ports and SI pins. The following are the reasons:

• Missing clock definition
• Due to missing output delay

Where do the multi-driven nets come from ?

            If we have a blackbox module in the design, Genus assumes all its ports as “inout” ports and this leads to the multi-driven nets warning. To resolve the issue, we need to at least define the port definitions for the blackbox module.

Synthesizing Unresolved References ?

            In Genus, unresolved references are instances that do not have any library or module definitions. It is important to distinguish unresolved references from timing models. Timing models, also known as blackboxes, are library elements that have timing information, but no functional descriptions.

            The ports of unresolved references are considered to be directionless. Unresolved references tend to cause numerous multi-drivers. Genus will maintain any logic leading into or out of the I/Os of unresolved references and treat them as unconstrained.

How to remove assign statements ?

            It is the constant input or output logic for the flop or port. For maintaining the constant logic at initial stage it is buffering 

remove_assigns_without_opt -buffer_or_inverter BUFX3